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| IS62LV5128LL 512K x 8 LOW POWER and LOW Vcc CMOS STATIC RAM FEATURES * Access times of 70, 85 ns * CMOS low power operation: -- 135 mW (typical) operating -- 16.5 W (typical) standby * Low data retention voltage: 2V (min.) * Output Enable (OE) and Chip Enable (CE) inputs for ease in applications * TTL compatible inputs and outputs * Fully static operation: -- No clock or refresh required * Single 2.7V (min) to 3.15V (max) VCC power supply * Available in 36-pin mini BGA ISSI DESCRIPTION (R) MAY 2001 The ISSI IS62LV5128LL is a low voltage, 524,288 words by 8 bits, CMOS SRAM. It is fabricated using ISSI's low voltage, six transistor (6T), CMOS technology. The device is targeted to satisfy the demands of the state-of-the-art technologies such as cell phones and pagers. When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Additionally, easy memory expansion is provided by using Chip Enable and Output Enable inputs, CE and OE. The active LOW Write Enable (WE) controls both writing and reading of the memory. The IS62LV5128LL is available in a 36-pin mini BGA package (8mm x 10mm). FUNCTIONAL BLOCK DIAGRAM A0-A18 DECODER 512K x 8 MEMORY ARRAY VCC GND I/O DATA CIRCUIT I/O0-I/O7 COLUMN I/O CE OE WE CONTROL CIRCUIT ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. (c) Copyright 2001, Integrated Silicon Solution, Inc. Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. D 05/04/01 1 IS62LV5128LL PIN CONFIGURATION 36-pin mini BGA (B) 1 2 3 4 5 6 ISSI PIN DESCRIPTIONS A0-A18 CE OE WE I/O0-I/O7 Address Inputs Chip Enable Input Output Enable Input Write Enable Input Input/Output No Connection Power Ground (R) A B C D E F G H A0 I/O4 I/O5 GND Vcc I/O6 I/O7 A9 A1 A2 NC WE NC A3 A4 A5 A6 A7 A8 I/O0 I/O1 Vcc GND NC Vcc GND A18 OE A10 CE A11 A17 A16 A12 A15 A13 I/O2 I/O3 A14 TRUTH TABLE Mode Not Selected Output Disabled Read Write WE X H H L CE H L L L OE X H L X I/O Operation High-Z High-Z DOUT DIN Vcc Current ISB1, ISB2 ICC ICC ICC OPERATING RANGE Range Commercial Industrial Ambient Temperature 0C to +70C -40C to +85C VCC Min. 2.7V 2.7V VCC Max. 3.15V 3.15V 2 Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. D 05/04/01 IS62LV5128LL ABSOLUTE MAXIMUM RATINGS(1) Symbol VTERM VCC TBIAS TSTG PT Parameter Terminal Voltage with Respect to GND Vcc related to GND Temperature Under Bias Storage Temperature Power Dissipation Value -0.5 to Vcc + 0.3 -0.3 to +3.3 -40 to +85 -65 to +150 1 Unit V V C C W ISSI (R) Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. CAPACITANCE(1,2) Symbol CIN COUT Parameter Input Capacitance Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 6 8 Unit pF pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25C, f = 1 MHz, Vcc = 3.0V. DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Symbol Parameter VOH VOL VIH VIL ILI ILO Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage(1) Input Leakage Output Leakage Test Conditions VCC = 3.0V, IOH = -1.0 mA VCC = 3.0V, IOL = 2.1 mA Min. 2.2 -- 2.2 -0.2 -1 -1 Max. -- 0.4 VCC + 0.3 0.4 1 1 Unit V V V V A A GND VIN VCC GND VOUT VCC, OUTPUTS Disabled Note: 1. VIL = -2.0V for pulse width less than 10 ns. Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. D 05/04/01 3 IS62LV5128LL POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) -70 Symbol Parameter ICC Vcc Dynamic Operating Supply Current Operating Supply Current TTL Standby Current (TTL Inputs) CMOS Standby Current (CMOS Inputs) Test Conditions VCC = Max., CE = VIL IOUT = 0 mA, f = fMAX VCC = Max., IOUT = 0 mA, f = 0 VCC = Max., VIN = VIH or VIL, CE1 VIH, f = 0 VCC = Max., f = 0 CE1 VCC - 0.2V, or VIN VCC - 0.2V, VIN 0.2V Com. Ind. Com. Ind. Com. Ind. Com. Ind. Min. -- -- -- -- -- -- -- -- Max. 40 45 5 5 0.4 1.0 10 10 Min. -- -- -- -- -- -- -- -- -85 ISSI Max. 35 40 5 5 0.4 1.0 10 10 (R) Unit mA ICC1 ISB1 mA mA ISB2 A Note: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) -70 Symbol Parameter Read Cycle Time Address Access Time Output Hold Time CE Access Time OE Access Time (2) -85 Max. -- 70 -- 70 35 25 -- -- 25 Min. 85 -- 15 -- -- -- 5 10 0 Max. -- 85 -- 85 40 25 -- -- 25 Unit ns ns ns ns ns ns ns ns ns Min. 70 -- 10 -- -- -- 5 10 0 tRC tAA tOHA tACE tDOE tHZOE tLZCE tLZOE(2) (2) (2) OE to High-Z Output OE to Low-Z Output CE to Low-Z Output CE to High-Z Output tHZCE Notes: 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0.4V to 2.2V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage. Not 100% tested. 4 Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. D 05/04/01 IS62LV5128LL AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0.4V to 2.2V 5 ns 1.5V See Figures 1 and 2 ISSI (R) AC TEST LOADS 3070 2.8V 2.8V 3070 OUTPUT 30 pF Including jig and scope 3150 OUTPUT 5 pF Including jig and scope 3150 Figure 1 Figure 2 Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. D 05/04/01 5 IS62LV5128LL AC WAVEFORMS READ CYCLE NO. 1(1,2) ISSI (R) tRC ADDRESS tAA tOHA tOHA DATA VALID DOUT READ CYCLE NO. 2(1,3) tRC ADDRESS tAA tOHA OE tDOE tHZOE CE tACE tLZCE tLZOE tHZCE DATA VALID DOUT HIGH-Z Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE = VIL. 3. Address is valid prior to or coincident with CE LOW transitions. 6 Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. D 05/04/01 IS62LV5128LL ISSI -70 -85 Max. -- -- -- -- -- -- -- -- 33 -- Min. 85 70 70 0 0 60 35 0 -- 5 Max. -- -- -- -- -- -- -- -- 35 -- Unit ns ns ns ns ns ns ns ns ns ns Min. 70 65 65 0 0 60 30 0 -- 5 (R) WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range, Standard and Low Power) Symbol Parameter Write Cycle Time CE to Write End Address Setup Time to Write End Address Hold from Write End Address Setup Time WE Pulse Width Data Setup to Write End Data Hold from Write End WE LOW to High-Z Output WE HIGH to Low-Z Output tWC tSCE tAW tHA tSA tPWE(4) tSD tHD tHZWE(2) tLZWE(2) Notes: 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0.4V to 2.2V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage. Not 100% tested. 3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. 4. Tested with OE HIGH. AC WAVEFORMS WRITE CYCLE NO. 1 (CE Controlled, OE = HIGH or LOW) tWC ADDRESS tSCE tHA CE tAW WE tSA tHZWE tPWE(4) tLZWE HIGH-Z DOUT DATA UNDEFINED tSD tHD DIN DATA-IN VALID Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. D 05/04/01 7 IS62LV5128LL WRITE CYCLE NO. 2 (WE Controlled: OE is HIGH During Write Cycle) tWC ISSI (R) ADDRESS OE tSCE tHA CE tAW tPWE1, 2 tSA tHZWE HIGH-Z WE tLZWE DOUT DATA UNDEFINED tSD tHD DIN DATA-IN VALID WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle) tWC ADDRESS OE tSCE tHA CE tAW tPWE1, 2 tSA tHZWE HIGH-Z WE tLZWE DOUT DATA UNDEFINED tSD tHD DIN DATA-IN VALID 8 Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. D 05/04/01 IS62LV5128LL DATA RETENTION SWITCHING CHARACTERISTICS Symbol VDR IDR tSDR tRDR Parameter Vcc for Data Retention Data Retention Current Data Retention Setup Time Recovery Time Test Condition See Data Retention Waveform Vcc = 2.0V, CE Vcc - 0.2V See Data Retention Waveform See Data Retention Waveform Com. Ind. Min. 1.5 -- -- 0 tRC ISSI Max. 3.15 10 10 -- -- Unit V A A ns ns (R) DATA RETENTION WAVEFORM (CE Controlled) tSDR VCC Data Retention Mode tRDR 2.7V 2.0V VDR CE VCC - 0.2V CE GND Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. D 05/04/01 9 IS62LV5128LL ORDERING INFORMATION Commercial Range: 0C to +70C Speed (ns) Order Part No. 70 85 IS62LV5128LL-70B IS62LV5128LL-85B Package mini BGA (8mm x 10mm) mini BGA (8mm x 10mm) ISSI (R) Industrial Range: -40C to +85C Speed (ns) Order Part No. 70 85 IS62LV5128LL-70BI IS62LV5128LL-85BI Package mini BGA (8mm x 10mm) mini BGA (8mm x 10mm) ISSI (R) Integrated Silicon Solution, Inc. 2231 Lawson Lane Santa Clara, CA 95054 Tel: 1-800-379-4774 Fax: (408) 588-0806 E-mail: sales@issi.com www.issi.com 10 Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. D 05/04/01 |
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